Assignment No 1 [with minimum answer]
[Should be submitted
in separate homework notebook of 100 pages by 31st January, 2013]
1.
What is Machine Status Word (MSW) of
80386? Draw its format.
Ans:
Figure : Control Register 0 ( Machine Status Word ) of 80386
PG (Paging Enable, bit 31)
The PG bit is set to enable the on-chip paging unit. It is
reset to disable the on-chip paging unit.
R (reserved, bit 4)
This bit is reserved by Intel. When loading CR0 care should
be taken to not alter the value of this bit.
TS (Task Switched, bit 3)
TS is automatically set whenever a task switch operation is
performed. If TS is set, a coprocessor ESCape opcode will cause a Coprocessor
Not Available trap (exception 7). The trap handler typically saves the Intel387
DX coprocessor context belonging to a previous task, loads the Intel387 DX
coprocessor state belonging to the current task, and clears the TS bit before
returning to the faulting coprocessor opcode.
EM (Emulate Coprocessor, bit 2)
The EMulate coprocessor bit is set to cause all coprocessor
opcodes to generate a Coprocessor Not Available fault (exception 7). It is
reset to allow coprocessor opcodes to be executed on an actual Intel387 DX
coprocessor. Note that theWAIT opcode is not affected by the EM bit setting.
MP (Monitor Coprocessor, bit 1)
The MP bit is used in conjunction with the TS bit to
determine if the WAIT opcode will generate a Coprocessor Not Available fault
(exception 7) when TS e 1. When both MP e 1 and TS e 1, the WAIT opcode
generates a trap. Otherwise, the WAIT opcode does not generate a trap. Note
that TS is automatically set whenever a task switch operation is performed.
PE (Protection Enable, bit 0)
The PE bit is set to enable the Protected Mode. If PE is
reset, the processor operates again in Real Mode. PE may be set by loading MSW
or CR0. PE can be reset only by a load into CR0. Resetting the PE bit is
typically part of a longer instruction sequence needed for proper transition from
Protected Mode to Real Mode.
2.
With the help of block diagram
explain the architecture of 80386.
Ans:
Figure : 80386 Architecture block Diagram
[Explanation should include around
one sentence about each block in above figure.]
3.
What is the function of BE0 to BE3
signal in 80386?
Ans:
The
386 address bus consists of the A2-A31 address lines and the byte enable lines
BE0# - BE3#. The BE0#-BE3# lines are
decoded from internal address signals A0 and A1 and function very similarly to
the way A0 and BHE function in an 8086 or 80286 system. The 80386 has a 32-bit data bus, so memory can
be set up as four byte-wide banks. The
BE0# - BE3# signals function as enables for the four banks. These individual enables allow the 386 to
transfer bytes, words, or double words to and from memory. Incidentally, the # symbol after the BE
signal names indicates that these signals are active low.
[Draw table of mapping A0, A1 with this lines]
4.
Explain BIU of 80386.
Ans:
[Draw part of architecture corresponding to Bus Interface.]
[Explain all pins connected to BIU.]
5.
Explain interrupt pins of 80386.
Ans:
1. INTR: INTERRUPT REQUEST is a maskable input that
signals the 80386 to suspend execution of the current program and execute an interrupt
acknowledge function.
2. NMI: NON-MASKABLE INTERRUPT REQUEST is a
non-maskable input that signals the 80386 to suspend execution of the current program
and execute an interrupt acknowledge function.
3. RESET: RESET suspends any operation in progress and
places the 80386 in a known reset state. See Interrupt Signals for additional information.
6.
Explain debug registers in 80386.
Ans:
The
six programmer accessible debug registers provide on-chip support for
debugging. Debug Registers DR0- specify
the four linear breakpoints. The Debug Control Register DR7 is used to set the
breakpoints and the Debug Status Register DR6, displays the current state of
the breakpoints.
7.
Explain Difference between 8086 and
80386.
Ans:
[Find out at least 8 points]
